1. Field of the Invention
The present invention relates to a data input circuit for a semiconductor memory device, and more particularly, to a data input circuit including an echo clock generator which reduces the clock cycle time in a synchronous semiconductor memory device. When this circuit is used in a synchronous dynamic random access memory (SDRAM), it may be called a Double Data Rate SDRAM (DDR-SDRAM). The circuit also may be used in other types of DRAM, and in other memory interfaces and memory devices such as static RAM (SRAM), flash memory, ferro-electric RAM (FRAM), and the like.
2. Description of the Related Art
In general, a computer system includes a central processing unit (CPU) for executing instructions for a given job, and a main memory for storing data and programs required by the CPU. Thus, in order to improve the performance of the computer system, it is necessary to improve the operating speed of the CPU and reduce the access time to the main memory. Accordingly, a double data rate synchronous dynamic random access memory (DDR-SDRAM) has been developed, which operates under the control of a system clock so that the main memory may be accessed very quickly.
FIG. 1 is a block diagram of a conventional data input/output circuit, in which data from an external source is input to a memory device via a data input buffer.
FIG. 2 is a diagram showing the various times that limit the clock cycle time t.sub.CC in a conventional data input circuit. Here, CLK.sub.-- SYS represents the waveform of a system clock, CLK.sub.-- CNTR represents the waveform of the system clock input to a memory controller, CLK.sub.-- DRAM represents the waveform of the system clock input to a DRAM, DATA.sub.-- DRAM represents data output from the DRAM, and DATA.sub.-- CNTR represents data output by the controller. CLK.sub.-- CNTR and CLK.sub.-- DRAM are the same as the system clock CLK.sub.-- SYS, but they are skewed because of the physical distances between the source that generates CLK.sub.-- SYS, the controller, and the DRAM.
Generally, the operation of the SDRAM is controlled in response to a clock signal generated by a system clock. Referring to FIG. 2, it may be seen that the clock cycle time t.sub.CC of the SDRAM is restricted by various factors. The clock cycle time t.sub.CC is determined and limited by the sum of the following times: the time difference t.sub.SW between the minimum time required for a writing operation of the memory and a clock cycle of the data input to a data controller, the time t.sub.AC from the clock synchronization to a data output, the time t.sub.FL required for transferring data from a memory to a controller, and a data set-up time t.sub.SS by the controller.
Therefore, t.sub.CC imposes a limitation on the system, in that t.sub.CC must be greater than the sum of t.sub.SW, t.sub.AC, t.sub.FL, and t.sub.SS. These limitations make it difficult to implement a SDRAM having a frequency of 300 MHz or greater using a conventional data input circuit.